The present invention relates generally to computer software for the design of semiconductor chips. More particularly, it relates to a method of processing data for analyzing a chip design stored in a computer memory.
In the field of semiconductor chip design and particularly very large scale integration (VLSI) chip design, a design may be stored in a computer memory for analysis. For example, the designer may wish to test the current or signal response through particular metal segments or conductors in the design. The individual nodes, signals, components, conductors, and other information are stored as a computer model in the computer database and used for design calculations and testing.
The computer model may include cross-references to save memory. For example, sometimes a particular series of components may be repeated in the design. The design may represent these related components in a single cell and store the cell to memory. Wherever the cell appears in the design, the computer model may merely have a reference to it, rather than storing all of its information every time it appears. This model is referred to as a hierarchical design, as opposed to a flat data representation. The hierarchical model may extend to groups of cells, and groups of groups, etc. as called for by the design. Wherever a series of items is repeated, the computer model may store the data in a hierarchy of cross-references.
One difficulty with the hierarchical model is that it is cumbersome and time-consuming to traverse. It requires multiple cross-references, increasing the time required to perform an analysis of the design. The alternative design model is the flat data representation, in which every element of the design is stored in full every time it appears in the design. The same data is stored multiple times because there are no cross-references. The flat data representation requires less time for analysis, but it is impractical to use because it requires too much storage memory to represent the entire design.
Another problem with analysis of circuit designs is that a particular design portion under test may have multiple paths between two nodes. For example, an electronic computer-aided design (E-CAD) tool may be run on the circuit design to analyze particular characteristics of a design portion, such as current along a specified path. The E-CAD tool retrieves the information from the design stored in memory, traversing the hierarchy as necessary. In its analysis, the E-CAD tool may need to traverse all of the paths between two nodes to ensure that it has analyzed each path. At the same time, the tool needs to make sure it does not analyze the same path twice, by looping back for example. Existing methods do not provide an efficient means of preventing the tool from analyzing the same portion of the design twice.
What is needed is a more efficient method for storing and processing chip design data to decrease required processing time without significantly affecting memory storage. What is also needed is a more efficient means of analyzing hierarchical data using a circuit analysis tool. What is also needed is a more efficient means of avoiding looping in the analysis of the design.
A method is disclosed for storing, for example, a very large scale integration (VLSI) circuit design in memory of a computer system and analyzing the design using an electronic computer-aided design (E-CAD) tool. The design may include hierarchical cells for repeated elements and groups of elements. A data structure is created to represent a specified portion of the circuit, such as a signal between two nodes. For each net in the specified portion, the data structure creates a node that stores a name, an address pointer to the underlying data in the circuit model, and address pointers to adjoining edges in the data structure. For each device between nets, the data structure creates an edge that stores a name, an address pointer to the underlying cell information in the circuit model, and address pointers to adjoining nodes. Also, the data structure stores an indicator showing whether each node or edge in the signal has been analyzed.
The circuit design is analyzed on a signal-by-signal basis using the E-CAD tool. The method selects a signal for analysis, creates a flat data representation for the signal, and stores it in memory. The E-CAD tool then performs its analysis on the flat representation and records the results in its ordinary operation. When the signal analysis is complete, the flat representation is deleted from memory, and other signals may be analyzed in turn.